![]() The work is supported, and formulated using very high speed integrated circuit hardware description language (VHDL) programming in Xilinx ISE 14.7 software. The concept of this design is programmable and can be extended to n-bit based on the applications. The novelty of the work is that the design is scalable and can be extended based on the requirements of the systems which is synthesized and experimentally verified on the Zynq-7000 field programmable gate array (FPGA) board. The article proposes the hardware chip design and simulation of two 5-bit LFSR modules used for the gold sequence generator applicable for the communication systems. The motivation of the work is to generate the Gold code sequence by the integration of two LFSR. A vector with entries would initialize the shift register. An LFSR of length m consists of m stages numbered, each capable of storing one bit, and a clock controlling data exchange. The hardware chip design and performance estimation of the LFSR is the problem for specific communication system. A linear feedback shift register (LFSR) is a shift register whose input bit is the output of a linear function of two or more of its previous states (taps). ![]() The LFSR is used in chip hardware for high-speed operations, error control, and the generation of pseudo-random numbers. There are simple shift register-based n-bit counters with a few XOR gates that behave pseudo-randomly. Linear feedback shift register (LFSR) is the basic building block of the communication system used in different coding, error detection and correction codes, such as gold, low-density parity check (LDPC), polar, and turbo codes.
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